176 lines
6.4 KiB
C
176 lines
6.4 KiB
C
#ifndef __W25QXX_QSPI_H
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#define __W25QXX_QSPI_H
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/* Definition for QSPI clock resources */
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#define QSPI_CLK_ENABLE() __HAL_RCC_QSPI_CLK_ENABLE()
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#define QSPI_CLK_DISABLE() __HAL_RCC_QSPI_CLK_DISABLE()
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#define QSPI_CS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE()
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#define QSPI_CLK_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
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#define QSPI_BK1_D0_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
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#define QSPI_BK1_D1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
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#define QSPI_BK1_D2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
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#define QSPI_BK1_D3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
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#define QSPI_MDMA_CLK_ENABLE() __HAL_RCC_MDMA_CLK_ENABLE()
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#define QSPI_FORCE_RESET() __HAL_RCC_QSPI_FORCE_RESET()
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#define QSPI_RELEASE_RESET() __HAL_RCC_QSPI_RELEASE_RESET()
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/* Definition for QSPI Pins */
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#define QSPI_CS_PIN GPIO_PIN_6
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#define QSPI_CS_GPIO_PORT GPIOG
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#define QSPI_CLK_PIN GPIO_PIN_2
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#define QSPI_CLK_GPIO_PORT GPIOB
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#define QSPI_BK1_D0_PIN GPIO_PIN_8
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#define QSPI_BK1_D0_GPIO_PORT GPIOF
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#define QSPI_BK1_D1_PIN GPIO_PIN_9
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#define QSPI_BK1_D1_GPIO_PORT GPIOF
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#define QSPI_BK1_D2_PIN GPIO_PIN_7
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#define QSPI_BK1_D2_GPIO_PORT GPIOF
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#define QSPI_BK1_D3_PIN GPIO_PIN_6
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#define QSPI_BK1_D3_GPIO_PORT GPIOF
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/* MT25TL01GHBA8ESF Micron memory */
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/* Size of the flash */
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#define QSPI_FLASH_SIZE 25
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#define QSPI_PAGE_SIZE 256
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/* Reset Operations */
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#define RESET_ENABLE_CMD 0x66
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#define RESET_MEMORY_CMD 0x99
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/* Identification Operations */
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#define READ_ID_CMD 0x90
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#define READ_ID_CMD2 0x9F
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#define MULTIPLE_IO_READ_ID_CMD 0xAF
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#define READ_SERIAL_FLASH_DISCO_PARAM_CMD 0x5A
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/* Read Operations */
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#define READ_CMD 0x03
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#define READ_4_BYTE_ADDR_CMD 0x13
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#define FAST_READ_CMD 0x0B
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#define FAST_READ_DTR_CMD 0x0D
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#define FAST_READ_4_BYTE_ADDR_CMD 0x0C
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#define DUAL_OUT_FAST_READ_CMD 0x3B
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#define DUAL_OUT_FAST_READ_DTR_CMD 0x3D
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#define DUAL_OUT_FAST_READ_4_BYTE_ADDR_CMD 0x3C
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#define DUAL_INOUT_FAST_READ_CMD 0xBB
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#define DUAL_INOUT_FAST_READ_DTR_CMD 0xBD
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#define DUAL_INOUT_FAST_READ_4_BYTE_ADDR_CMD 0xBC
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#define QUAD_OUT_FAST_READ_CMD 0x6B
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#define QUAD_OUT_FAST_READ_DTR_CMD 0x6D
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#define QUAD_OUT_FAST_READ_4_BYTE_ADDR_CMD 0x6C
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#define QUAD_INOUT_FAST_READ_CMD 0xEB
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#define QUAD_INOUT_FAST_READ_DTR_CMD 0xED
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#define QUAD_INOUT_FAST_READ_4_BYTE_ADDR_CMD 0xEC
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/* Write Operations */
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#define WRITE_ENABLE_CMD 0x06
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#define WRITE_DISABLE_CMD 0x04
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/* Register Operations */
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#define READ_STATUS_REG1_CMD 0x05
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#define WRITE_STATUS_REG1_CMD 0x01
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#define READ_STATUS_REG2_CMD 0x35
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#define WRITE_STATUS_REG2_CMD 0x31
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#define READ_STATUS_REG3_CMD 0x15
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#define WRITE_STATUS_REG3_CMD 0x11
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#define READ_LOCK_REG_CMD 0xE8
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#define WRITE_LOCK_REG_CMD 0xE5
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#define READ_FLAG_STATUS_REG_CMD 0x70
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#define CLEAR_FLAG_STATUS_REG_CMD 0x50
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#define READ_NONVOL_CFG_REG_CMD 0xB5
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#define WRITE_NONVOL_CFG_REG_CMD 0xB1
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#define READ_VOL_CFG_REG_CMD 0x85
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#define WRITE_VOL_CFG_REG_CMD 0x81
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#define READ_ENHANCED_VOL_CFG_REG_CMD 0x65
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#define WRITE_ENHANCED_VOL_CFG_REG_CMD 0x61
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#define READ_EXT_ADDR_REG_CMD 0xC8
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#define WRITE_EXT_ADDR_REG_CMD 0xC5
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/* Program Operations */
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#define PAGE_PROG_CMD 0x02
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#define PAGE_PROG_4_BYTE_ADDR_CMD 0x12
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#define DUAL_IN_FAST_PROG_CMD 0xA2
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#define EXT_DUAL_IN_FAST_PROG_CMD 0xD2
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#define QUAD_IN_FAST_PROG_CMD 0x32
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#define EXT_QUAD_IN_FAST_PROG_CMD 0x12 /*0x38*/
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#define QUAD_IN_FAST_PROG_4_BYTE_ADDR_CMD 0x34
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/* Erase Operations */
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#define SUBSECTOR_ERASE_CMD 0x20
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#define SUBSECTOR_ERASE_4_BYTE_ADDR_CMD 0x21
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#define SECTOR_ERASE_CMD 0xD8
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#define SECTOR_ERASE_4_BYTE_ADDR_CMD 0xDC
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#define BULK_ERASE_CMD 0xC7
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#define PROG_ERASE_RESUME_CMD 0x7A
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#define PROG_ERASE_SUSPEND_CMD 0x75
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/* One-Time Programmable Operations */
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#define READ_OTP_ARRAY_CMD 0x4B
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#define PROG_OTP_ARRAY_CMD 0x42
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/* 4-byte Address Mode Operations */
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#define ENTER_4_BYTE_ADDR_MODE_CMD 0xB7
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#define EXIT_4_BYTE_ADDR_MODE_CMD 0xE9
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/* Quad Operations */
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#define ENTER_QUAD_CMD 0x35
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#define EXIT_QUAD_CMD 0xF5
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/* Default dummy clocks cycles */
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#define DUMMY_CLOCK_CYCLES_READ 8
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#define DUMMY_CLOCK_CYCLES_READ_QUAD 8
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#define DUMMY_CLOCK_CYCLES_READ_DTR 6
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#define DUMMY_CLOCK_CYCLES_READ_QUAD_DTR 8
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/* End address of the QSPI memory */
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#define QSPI_END_ADDR (1 << QSPI_FLASH_SIZE)
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/* Size of buffers */
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#define BUFFERSIZE (COUNTOF(aTxBuffer) - 1)
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/* Exported macro ------------------------------------------------------------*/
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#define COUNTOF(__BUFFER__) (sizeof(__BUFFER__) / sizeof(*(__BUFFER__)))
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/* Exported functions ------------------------------------------------------- */
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extern void w25qxx_qspi_setup(void);
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extern unsigned short w25qxx_qspi_read_id(void);
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void W25QXX_Init(void);
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void W25QXX_Qspi_Enable(void);
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void W25QXX_Qspi_Disable(void);
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unsigned short W25QXX_ReadID(void);
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unsigned char W25QXX_ReadSR(unsigned char regno);
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void W25QXX_Write_SR(unsigned char regno,unsigned char sr);
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void W25QXX_Write_Enable(void);
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void W25QXX_Write_Disable(void);
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void W25QXX_Write_NoCheck(unsigned char* pBuffer,unsigned int WriteAddr,unsigned short NumByteToWrite);//дflash,²»Ð£Ñé
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void W25QXX_Read(unsigned char* pBuffer,unsigned int ReadAddr,unsigned short NumByteToRead);
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void W25QXX_Write(unsigned char* pBuffer,unsigned int WriteAddr,unsigned short NumByteToWrite);
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void W25QXX_Erase_Chip(void);
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void W25QXX_Erase_Sector(unsigned int addr);
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void W25QXX_Wait_Busy(void);
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#endif
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