#ifndef __W25QXX_QSPI_H #define __W25QXX_QSPI_H /* Definition for QSPI clock resources */ #define QSPI_CLK_ENABLE() __HAL_RCC_QSPI_CLK_ENABLE() #define QSPI_CLK_DISABLE() __HAL_RCC_QSPI_CLK_DISABLE() #define QSPI_CS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE() #define QSPI_CLK_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE() #define QSPI_BK1_D0_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE() #define QSPI_BK1_D1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE() #define QSPI_BK1_D2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE() #define QSPI_BK1_D3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE() #define QSPI_MDMA_CLK_ENABLE() __HAL_RCC_MDMA_CLK_ENABLE() #define QSPI_FORCE_RESET() __HAL_RCC_QSPI_FORCE_RESET() #define QSPI_RELEASE_RESET() __HAL_RCC_QSPI_RELEASE_RESET() /* Definition for QSPI Pins */ #define QSPI_CS_PIN GPIO_PIN_6 #define QSPI_CS_GPIO_PORT GPIOG #define QSPI_CLK_PIN GPIO_PIN_2 #define QSPI_CLK_GPIO_PORT GPIOB #define QSPI_BK1_D0_PIN GPIO_PIN_8 #define QSPI_BK1_D0_GPIO_PORT GPIOF #define QSPI_BK1_D1_PIN GPIO_PIN_9 #define QSPI_BK1_D1_GPIO_PORT GPIOF #define QSPI_BK1_D2_PIN GPIO_PIN_7 #define QSPI_BK1_D2_GPIO_PORT GPIOF #define QSPI_BK1_D3_PIN GPIO_PIN_6 #define QSPI_BK1_D3_GPIO_PORT GPIOF /* MT25TL01GHBA8ESF Micron memory */ /* Size of the flash */ #define QSPI_FLASH_SIZE 25 #define QSPI_PAGE_SIZE 256 /* Reset Operations */ #define RESET_ENABLE_CMD 0x66 #define RESET_MEMORY_CMD 0x99 /* Identification Operations */ #define READ_ID_CMD 0x90 #define READ_ID_CMD2 0x9F #define MULTIPLE_IO_READ_ID_CMD 0xAF #define READ_SERIAL_FLASH_DISCO_PARAM_CMD 0x5A /* Read Operations */ #define READ_CMD 0x03 #define READ_4_BYTE_ADDR_CMD 0x13 #define FAST_READ_CMD 0x0B #define FAST_READ_DTR_CMD 0x0D #define FAST_READ_4_BYTE_ADDR_CMD 0x0C #define DUAL_OUT_FAST_READ_CMD 0x3B #define DUAL_OUT_FAST_READ_DTR_CMD 0x3D #define DUAL_OUT_FAST_READ_4_BYTE_ADDR_CMD 0x3C #define DUAL_INOUT_FAST_READ_CMD 0xBB #define DUAL_INOUT_FAST_READ_DTR_CMD 0xBD #define DUAL_INOUT_FAST_READ_4_BYTE_ADDR_CMD 0xBC #define QUAD_OUT_FAST_READ_CMD 0x6B #define QUAD_OUT_FAST_READ_DTR_CMD 0x6D #define QUAD_OUT_FAST_READ_4_BYTE_ADDR_CMD 0x6C #define QUAD_INOUT_FAST_READ_CMD 0xEB #define QUAD_INOUT_FAST_READ_DTR_CMD 0xED #define QUAD_INOUT_FAST_READ_4_BYTE_ADDR_CMD 0xEC /* Write Operations */ #define WRITE_ENABLE_CMD 0x06 #define WRITE_DISABLE_CMD 0x04 /* Register Operations */ #define READ_STATUS_REG1_CMD 0x05 #define WRITE_STATUS_REG1_CMD 0x01 #define READ_STATUS_REG2_CMD 0x35 #define WRITE_STATUS_REG2_CMD 0x31 #define READ_STATUS_REG3_CMD 0x15 #define WRITE_STATUS_REG3_CMD 0x11 #define READ_LOCK_REG_CMD 0xE8 #define WRITE_LOCK_REG_CMD 0xE5 #define READ_FLAG_STATUS_REG_CMD 0x70 #define CLEAR_FLAG_STATUS_REG_CMD 0x50 #define READ_NONVOL_CFG_REG_CMD 0xB5 #define WRITE_NONVOL_CFG_REG_CMD 0xB1 #define READ_VOL_CFG_REG_CMD 0x85 #define WRITE_VOL_CFG_REG_CMD 0x81 #define READ_ENHANCED_VOL_CFG_REG_CMD 0x65 #define WRITE_ENHANCED_VOL_CFG_REG_CMD 0x61 #define READ_EXT_ADDR_REG_CMD 0xC8 #define WRITE_EXT_ADDR_REG_CMD 0xC5 /* Program Operations */ #define PAGE_PROG_CMD 0x02 #define PAGE_PROG_4_BYTE_ADDR_CMD 0x12 #define DUAL_IN_FAST_PROG_CMD 0xA2 #define EXT_DUAL_IN_FAST_PROG_CMD 0xD2 #define QUAD_IN_FAST_PROG_CMD 0x32 #define EXT_QUAD_IN_FAST_PROG_CMD 0x12 /*0x38*/ #define QUAD_IN_FAST_PROG_4_BYTE_ADDR_CMD 0x34 /* Erase Operations */ #define SUBSECTOR_ERASE_CMD 0x20 #define SUBSECTOR_ERASE_4_BYTE_ADDR_CMD 0x21 #define SECTOR_ERASE_CMD 0xD8 #define SECTOR_ERASE_4_BYTE_ADDR_CMD 0xDC #define BULK_ERASE_CMD 0xC7 #define PROG_ERASE_RESUME_CMD 0x7A #define PROG_ERASE_SUSPEND_CMD 0x75 /* One-Time Programmable Operations */ #define READ_OTP_ARRAY_CMD 0x4B #define PROG_OTP_ARRAY_CMD 0x42 /* 4-byte Address Mode Operations */ #define ENTER_4_BYTE_ADDR_MODE_CMD 0xB7 #define EXIT_4_BYTE_ADDR_MODE_CMD 0xE9 /* Quad Operations */ #define ENTER_QUAD_CMD 0x35 #define EXIT_QUAD_CMD 0xF5 /* Default dummy clocks cycles */ #define DUMMY_CLOCK_CYCLES_READ 8 #define DUMMY_CLOCK_CYCLES_READ_QUAD 8 #define DUMMY_CLOCK_CYCLES_READ_DTR 6 #define DUMMY_CLOCK_CYCLES_READ_QUAD_DTR 8 /* End address of the QSPI memory */ #define QSPI_END_ADDR (1 << QSPI_FLASH_SIZE) /* Size of buffers */ #define BUFFERSIZE (COUNTOF(aTxBuffer) - 1) /* Exported macro ------------------------------------------------------------*/ #define COUNTOF(__BUFFER__) (sizeof(__BUFFER__) / sizeof(*(__BUFFER__))) /* Exported functions ------------------------------------------------------- */ extern void w25qxx_qspi_setup(void); extern unsigned short w25qxx_qspi_read_id(void); void W25QXX_Init(void); void W25QXX_Qspi_Enable(void); void W25QXX_Qspi_Disable(void); unsigned short W25QXX_ReadID(void); unsigned char W25QXX_ReadSR(unsigned char regno); void W25QXX_Write_SR(unsigned char regno,unsigned char sr); void W25QXX_Write_Enable(void); void W25QXX_Write_Disable(void); void W25QXX_Write_NoCheck(unsigned char* pBuffer,unsigned int WriteAddr,unsigned short NumByteToWrite);//дflash,²»Ð£Ñé void W25QXX_Read(unsigned char* pBuffer,unsigned int ReadAddr,unsigned short NumByteToRead); void W25QXX_Write(unsigned char* pBuffer,unsigned int WriteAddr,unsigned short NumByteToWrite); void W25QXX_Erase_Chip(void); void W25QXX_Erase_Sector(unsigned int addr); void W25QXX_Wait_Busy(void); #endif