1、【增加】RT-Thread 系统 Demo。

Signed-off-by: armink <armink.ztl@gmail.com>

demos/os/rtthread/stm32f4xx/components/cm_backtrace/cmb_cfg.h

@@ -0,0 +1,45 @@
+/*
+ * This file is part of the CmBacktrace Library.
+ *
+ * Copyright (c) 2016, Armink, <armink.ztl@gmail.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * 'Software'), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED 'AS IS', WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Function: It is the configure head file for this library.
+ * Created on: 2016-12-15
+ */
+
+#ifndef _CMB_CFG_H_
+#define _CMB_CFG_H_
+
+#include <rtthread.h>
+/* print line, must config by user */
+#define cmb_println(...)               rt_kprintf(__VA_ARGS__);rt_kprintf("\r\n")
+/* enable OS platform */
+#define CMB_USING_OS_PLATFORM
+/* OS platform type, must config when CMB_USING_OS_PLATFORM is enable */
+#define CMB_OS_PLATFORM_TYPE           CMB_OS_PLATFORM_RTT
+/* cpu platform type, must config by user */
+#define CMB_CPU_PLATFORM_TYPE          CMB_CPU_ARM_CORTEX_M4
+/* enable dump stack information */
+#define CMB_USING_DUMP_STACK_INFO
+/* language of print information */
+#define CMB_PRINT_LANGUAGE             CMB_PRINT_LANUUAGE_ENGLISH
+#endif /* _CMB_CFG_H_ */

demos/os/rtthread/stm32f4xx/components/others/bsp.c

@@ -0,0 +1,205 @@
+/*
+*********************************************************************************************************
+*                                             INCLUDE FILES
+*********************************************************************************************************
+*/
+#define  BSP_MODULE
+
+#include <bsp.h>
+/*
+*********************************************************************************************************
+*                                            LOCAL TABLES
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*                                       LOCAL GLOBAL VARIABLES
+*********************************************************************************************************
+*/
+
+/*
+*********************************************************************************************************
+*                                      LOCAL FUNCTION PROTOTYPES
+*********************************************************************************************************
+*/
+
+/** This function will initial STM32 board**/
+void rt_hw_board_init()
+{
+    BSP_Init();
+    //add for finsh
+    stm32_hw_usart_init();
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+}
+
+/**
+ * RCC configuration
+ */
+static void RCC_Configuration(void)
+{
+	//下面是给各模块开启时钟
+	//启动GPIO
+	RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | \
+	                       RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | \
+	                       RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_GPIOG,
+	                       ENABLE);
+
+	//启动USART1时钟
+	RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
+	//启动USART2时钟
+	RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
+	//启动DMA时钟
+	RCC_APB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
+	/* Enable ADC1 and GPIOC clock */
+	RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);
+	/* Enable WWDG clock */
+	RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE);
+}
+
+/**
+ * NVIC Configuration
+ */
+static void NVIC_Configuration(void)
+{
+#if  defined(VECT_TAB_RAM)
+    // Set the Vector Table base location at 0x20000000
+    NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x00);
+#elif  defined(VECT_TAB_FLASH)
+    // Set the Vector Table base location at 0x08000000
+    NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x00);
+#elif defined(VECT_TAB_USER)
+    // Set the Vector Table base location by user
+    NVIC_SetVectorTable(NVIC_VectTab_FLASH, USER_VECTOR_TABLE);
+#endif
+
+}
+
+/**
+ * GPIO Configuration
+ */
+static void GPIO_Configuration(void)
+{
+	GPIO_InitTypeDef GPIO_InitStructure;
+
+	/* PA13:SWDIO PA14:SWCLK for debug, can't set to output mode */
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All & (~(GPIO_Pin_13 | GPIO_Pin_14));
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+    GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+    GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_All;
+    GPIO_Init(GPIOB, &GPIO_InitStructure);
+    GPIO_Init(GPIOC, &GPIO_InitStructure);
+    GPIO_Init(GPIOD, &GPIO_InitStructure);
+    GPIO_Init(GPIOE, &GPIO_InitStructure);
+    GPIO_Init(GPIOF, &GPIO_InitStructure);
+    GPIO_Init(GPIOG, &GPIO_InitStructure);
+
+	/******************系统运行LED指示灯配置*******************/
+	GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
+    GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+    GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_Init(GPIOB, &GPIO_InitStructure);
+}
+
+
+/**
+ * IWDG_Configuration
+ */
+static void IWDG_Configuration(void) 
+{
+    IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);
+    IWDG_SetPrescaler(IWDG_Prescaler_64);
+    IWDG_SetReload(1875);
+    IWDG_ReloadCounter();
+    IWDG_Enable();
+}
+
+/**
+ * feed IWDG dog
+ */
+void IWDG_Feed(void)
+{
+    IWDG_ReloadCounter();//reload
+}
+
+
+/**
+ * SysTick Configuration
+ */
+void  SysTick_Configuration(void)
+{
+    RCC_ClocksTypeDef  rcc_clocks;
+    rt_uint32_t         cnts;
+
+    RCC_GetClocksFreq(&rcc_clocks);
+
+    cnts = (rt_uint32_t)rcc_clocks.HCLK_Frequency / RT_TICK_PER_SECOND;
+    cnts = cnts / 8;
+
+    SysTick_Config(cnts);
+    SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK_Div8);
+}
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void rt_hw_timer_handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+void assert_failed(u8* file, u32 line)
+{
+    /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+    /* Infinite loop */
+    rt_kprintf("assert failed at %s:%d \n", file, line);
+    while (1) {
+    }
+}
+/*
+*********************************************************************************************************
+*                                     LOCAL CONFIGURATION ERRORS
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*                                               BSP_Init()
+*
+* Description : Initialize the Board Support Package (BSP).
+*
+* Argument(s) : none.
+*
+* Return(s)   : none.
+*
+* Caller(s)   : Application.
+*
+* Note(s)     : (1) This function SHOULD be called before any other BSP function is called.
+*********************************************************************************************************
+*/
+
+void  BSP_Init (void)
+{
+    RCC_Configuration();
+    NVIC_Configuration();
+    SysTick_Configuration();
+    GPIO_Configuration();
+//TODO  Now temporary comment this code, the official version will open his
+//     IWDG_Configuration();
+}
+

demos/os/rtthread/stm32f4xx/components/others/bsp.h

@@ -0,0 +1,98 @@
+
+#ifndef  BSP_PRESENT
+#define  BSP_PRESENT
+
+/*
+*********************************************************************************************************
+*                                                 EXTERNS
+*********************************************************************************************************
+*/
+
+
+/*
+*********************************************************************************************************
+*                                              INCLUDE FILES
+*********************************************************************************************************
+*/
+
+
+
+#include <stm32f4xx_conf.h>
+#include <rthw.h>
+#include <rtthread.h>
+#include "usart.h"
+
+/*
+*********************************************************************************************************
+*                                                 DEFINES
+*********************************************************************************************************
+*/
+/* board configuration */
+// <o> SDCard Driver <1=>SDIO sdcard <0=>SPI MMC card
+// 	<i>Default: 1
+#define STM32_USE_SDIO			0
+
+/* whether use board external SRAM memory */
+// <e>Use external SRAM memory on the board
+// 	<i>Enable External SRAM memory
+#define STM32_EXT_SRAM          0
+//	<o>Begin Address of External SRAM
+//		<i>Default: 0x68000000
+#define STM32_EXT_SRAM_BEGIN    0x68000000 /* the begining address of external SRAM */
+//	<o>End Address of External SRAM
+//		<i>Default: 0x68080000
+#define STM32_EXT_SRAM_END      0x68080000 /* the end address of external SRAM */
+// </e>
+
+#define STM32_SRAM_BEGIN        SRAM_BASE
+// <o> Internal SRAM memory size[Kbytes]
+//	<i>Default: 128
+#define STM32_SRAM_SIZE         128
+#define STM32_SRAM_END          (SRAM_BASE + STM32_SRAM_SIZE * 1024)
+
+#define VECT_TAB_FLASH                                     /* use Flash to store vector table */
+
+/* RT_USING_UART */
+#define RT_USING_UART1
+#define RT_UART_RX_BUFFER_SIZE	64
+
+#define LED_RUN_ON              GPIO_SetBits  (GPIOB,GPIO_Pin_12)  	   //RUN
+#define LED_RUN_OFF             GPIO_ResetBits(GPIOB,GPIO_Pin_12) 	   //RUN
+
+/*********************************************************************************************************/
+/**                                                 MACRO'S												 */
+/***********************************************************************************************************/
+
+
+/***********************************************************************************************************/
+/*                                               DATA TYPES												 */
+/***********************************************************************************************************/
+
+
+/**********************************************************************************************************
+*                                            GLOBAL VARIABLES
+**********************************************************************************************************/
+
+
+
+
+/*
+*********************************************************************************************************
+*                                           FUNCTION PROTOTYPES
+*********************************************************************************************************
+*/
+
+void BSP_Init(void);
+
+void rt_hw_board_init(void);
+void IWDG_Feed(void);
+void rt_hw_timer_handler(void);
+
+/*
+*********************************************************************************************************
+*                                           INTERRUPT SERVICES
+*********************************************************************************************************
+*/
+
+
+#endif                                                          /* End of module include.                               */

demos/os/rtthread/stm32f4xx/components/others/stm32f405xG.icf

@@ -0,0 +1,51 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/* 软件及硬件版本号存放地址 */
+define symbol __ICFEDIT_version_start__ = __ICFEDIT_intvec_start__ + 512;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = __ICFEDIT_intvec_start__;
+define symbol __ICFEDIT_region_ROM_end__   = 0x080FFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2001FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x2000;
+define symbol __ICFEDIT_size_heap__   = 0x2000;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_RAM1_start__ = 0x10000000;
+define symbol __region_RAM1_end__   = 0x1000FFFF;
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region RAM1_region  = mem:[from __region_RAM1_start__   to __region_RAM1_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { section .sram};
+place in RAM1_region  { readwrite  ,
+                        block CSTACK, block HEAP};
+
+/* armink add for e-boot serial command */
+keep { section IbootSerialCmdTab };
+
+/* armink add for wifi command dispather */
+keep { section RCSymTab };
+
+/* armink add for version storage */
+keep { section .version };
+place at address mem:__ICFEDIT_version_start__ { readonly section .version };
+
+/* armink add for finsh */
+keep { section FSymTab };
+keep { section VSymTab };

demos/os/rtthread/stm32f4xx/components/others/types.h

@@ -0,0 +1,33 @@
+
+#ifndef TYPES_H_
+#define TYPES_H_
+
+#include <stdint.h>
+#include <stddef.h>
+typedef int                             bool_t;      /**< boolean type */
+
+#ifndef TRUE
+	#define TRUE            1
+#endif
+
+#ifndef FALSE
+	#define FALSE           0
+#endif
+
+#ifndef NULL
+	#define NULL 0
+#endif
+
+#define success                  0
+#define fail                     1
+
+
+#ifndef disable
+    #define disable 0
+#endif
+
+#ifndef enable
+    #define enable 1
+#endif
+
+#endif /* TYPES_H_ */

demos/os/rtthread/stm32f4xx/components/others/utils.c

@@ -0,0 +1,30 @@
+#include "utils.h"
+
+/* current system status */
+static SystemStatus cur_system_status = SYSTEM_STATUS_INIT;
+
+
+/**
+ * System go to fault status.
+ */
+void system_go_to_fault_status(void){
+    cur_system_status = SYSTEM_STATUS_FAULT;
+}
+
+/**
+ * Set current system status.
+ *
+ * @param status system status
+ */
+void set_system_status(SystemStatus status){
+    cur_system_status = status;
+}
+
+/**
+ * Get current system status.
+ *
+ * @return current system status
+ */
+SystemStatus get_system_status(void){
+    return cur_system_status;
+}

demos/os/rtthread/stm32f4xx/components/others/utils.h

@@ -0,0 +1,20 @@
+#ifndef UTILS_H_
+#define UTILS_H_
+
+#include <stm32f4xx_conf.h>
+#include <rtthread.h>
+
+/* system status */
+typedef enum{
+    SYSTEM_STATUS_INIT,
+    SYSTEM_STATUS_RUN,
+    SYSTEM_STATUS_FAULT,
+    SYSTEM_STATUS_SLEEP,
+}SystemStatus;
+
+void Delay(vu32 nCount);
+void system_go_to_fault_status(void);
+void set_system_status(SystemStatus status);
+SystemStatus get_system_status(void);
+
+#endif /* UTILS_H_ */

demos/os/rtthread/stm32f4xx/components/rtt_uart/usart.c

@@ -0,0 +1,387 @@
+/*
+ * File      : usart.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      the first version
+ * 2010-03-29     Bernard      remove interrupt Tx and DMA Rx mode
+ * 2012-02-08     aozima       update for F4.
+ * 2012-07-28     aozima       update for ART board.
+ */
+
+#include "stm32f4xx_conf.h"
+#include "usart.h"
+#include "bsp.h"
+
+#include <rtdevice.h>
+
+/* UART GPIO define. */
+#define UART1_GPIO_TX       GPIO_Pin_9
+#define UART1_TX_PIN_SOURCE GPIO_PinSource9
+#define UART1_GPIO_RX       GPIO_Pin_10
+#define UART1_RX_PIN_SOURCE GPIO_PinSource10
+#define UART1_GPIO          GPIOA
+#define UART1_GPIO_RCC      RCC_AHB1Periph_GPIOA
+#define RCC_APBPeriph_UART1 RCC_APB2Periph_USART1
+#define UART1_TX_DMA        DMA1_Channel4
+#define UART1_RX_DMA        DMA1_Channel5
+
+#define UART2_GPIO_TX       GPIO_Pin_2
+#define UART2_TX_PIN_SOURCE GPIO_PinSource2
+#define UART2_GPIO_RX       GPIO_Pin_3
+#define UART2_RX_PIN_SOURCE GPIO_PinSource3
+#define UART2_GPIO          GPIOA
+#define UART2_GPIO_RCC      RCC_AHB1Periph_GPIOA
+#define RCC_APBPeriph_UART2 RCC_APB1Periph_USART2
+#define UART2_TX_DMA        DMA1_Channel4
+#define UART2_RX_DMA        DMA1_Channel5
+
+#define UART3_GPIO_TX       GPIO_Pin_8
+#define UART3_TX_PIN_SOURCE GPIO_PinSource8
+#define UART3_GPIO_RX       GPIO_Pin_9
+#define UART3_RX_PIN_SOURCE GPIO_PinSource9
+#define UART3_GPIO          GPIOD
+#define UART3_GPIO_RCC      RCC_AHB1Periph_GPIOD
+#define RCC_APBPeriph_UART3 RCC_APB1Periph_USART3
+#define UART3_TX_DMA        DMA1_Stream1
+#define UART3_RX_DMA        DMA1_Stream3
+
+/* STM32 uart driver */
+struct stm32_uart
+{
+    USART_TypeDef *uart_device;
+    IRQn_Type irq;
+};
+
+static rt_err_t stm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct stm32_uart *uart;
+    USART_InitTypeDef USART_InitStructure;
+
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+
+    uart = (struct stm32_uart *)serial->parent.user_data;
+
+    if (cfg->baud_rate == BAUD_RATE_9600)
+        USART_InitStructure.USART_BaudRate = 9600;
+    else if (cfg->baud_rate == BAUD_RATE_115200)
+        USART_InitStructure.USART_BaudRate = 115200;
+
+    if (cfg->data_bits == DATA_BITS_8)
+        USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+
+    if (cfg->stop_bits == STOP_BITS_1)
+        USART_InitStructure.USART_StopBits = USART_StopBits_1;
+    else if (cfg->stop_bits == STOP_BITS_2)
+        USART_InitStructure.USART_StopBits = USART_StopBits_2;
+
+    USART_InitStructure.USART_Parity = USART_Parity_No;
+    USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+    USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+    USART_Init(uart->uart_device, &USART_InitStructure);
+
+    /* Enable USART */
+    USART_Cmd(uart->uart_device, ENABLE);
+
+    return RT_EOK;
+}
+
+static rt_err_t stm32_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct stm32_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct stm32_uart *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        UART_DISABLE_IRQ(uart->irq);
+        /* disable interrupt */
+        USART_ITConfig(uart->uart_device, USART_IT_RXNE, DISABLE);
+        break;
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        UART_ENABLE_IRQ(uart->irq);
+        /* enable interrupt */
+        USART_ITConfig(uart->uart_device, USART_IT_RXNE, ENABLE);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int stm32_putc(struct rt_serial_device *serial, char c)
+{
+    struct stm32_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct stm32_uart *)serial->parent.user_data;
+
+    while (!(uart->uart_device->SR & USART_FLAG_TXE));
+    uart->uart_device->DR = c;
+
+    return 1;
+}
+
+static int stm32_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    struct stm32_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct stm32_uart *)serial->parent.user_data;
+
+    ch = -1;
+    if (uart->uart_device->SR & USART_FLAG_RXNE)
+    {
+        ch = uart->uart_device->DR & 0xff;
+    }
+
+    return ch;
+}
+
+static const struct rt_uart_ops stm32_uart_ops =
+{
+    stm32_configure,
+    stm32_control,
+    stm32_putc,
+    stm32_getc,
+};
+
+#if defined(RT_USING_UART1)
+/* UART1 device driver structure */
+struct stm32_uart uart1 =
+{
+    USART1,
+    USART1_IRQn,
+};
+struct rt_serial_device serial1;
+
+void USART1_IRQHandler(void)
+{
+    struct stm32_uart *uart;
+
+    uart = &uart1;
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+    if (USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET)
+    {
+        rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND);
+    }
+    if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET)
+    {
+        /* clear interrupt */
+        USART_ClearITPendingBit(uart->uart_device, USART_IT_TC);
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* RT_USING_UART1 */
+
+#if defined(RT_USING_UART2)
+/* UART2 device driver structure */
+struct stm32_uart uart2 =
+{
+    USART2,
+    USART2_IRQn,
+};
+struct rt_serial_device serial2;
+
+void USART2_IRQHandler(void)
+{
+    struct stm32_uart *uart;
+
+    uart = &uart2;
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+    if (USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET)
+    {
+        rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND);
+    }
+    if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET)
+    {
+        /* clear interrupt */
+        USART_ClearITPendingBit(uart->uart_device, USART_IT_TC);
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* RT_USING_UART2 */
+
+#if defined(RT_USING_UART3)
+/* UART3 device driver structure */
+struct stm32_uart uart3 =
+{
+    USART3,
+    USART3_IRQn,
+};
+struct rt_serial_device serial3;
+
+void USART3_IRQHandler(void)
+{
+    struct stm32_uart *uart;
+
+    uart = &uart3;
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+    if (USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET)
+    {
+        rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND);
+    }
+    if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET)
+    {
+        /* clear interrupt */
+        USART_ClearITPendingBit(uart->uart_device, USART_IT_TC);
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* RT_USING_UART3 */
+
+static void RCC_Configuration(void)
+{
+#ifdef RT_USING_UART1
+    /* Enable UART1 GPIO clocks */
+    RCC_AHB1PeriphClockCmd(UART1_GPIO_RCC, ENABLE);
+    /* Enable UART1 clock */
+    RCC_APB2PeriphClockCmd(RCC_APBPeriph_UART1, ENABLE);
+#endif /* RT_USING_UART1 */
+
+#ifdef RT_USING_UART2
+    /* Enable UART2 GPIO clocks */
+    RCC_AHB1PeriphClockCmd(UART2_GPIO_RCC, ENABLE);
+    /* Enable UART2 clock */
+    RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART2, ENABLE);
+#endif /* RT_USING_UART1 */
+
+#ifdef RT_USING_UART3
+    /* Enable UART3 GPIO clocks */
+    RCC_AHB1PeriphClockCmd(UART3_GPIO_RCC, ENABLE);
+    /* Enable UART3 clock */
+    RCC_APB1PeriphClockCmd(RCC_APBPeriph_UART3, ENABLE);
+#endif /* RT_USING_UART3 */
+}
+
+static void GPIO_Configuration(void)
+{
+    GPIO_InitTypeDef GPIO_InitStructure;
+
+    GPIO_InitStructure.GPIO_Mode  = GPIO_Mode_AF;
+    GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
+    GPIO_InitStructure.GPIO_PuPd  = GPIO_PuPd_UP;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
+
+#ifdef RT_USING_UART1
+    /* Configure USART1 Rx/tx PIN */
+    GPIO_InitStructure.GPIO_Pin = UART1_GPIO_RX | UART1_GPIO_TX;
+    GPIO_Init(UART1_GPIO, &GPIO_InitStructure);
+
+    /* Connect alternate function */
+    GPIO_PinAFConfig(UART1_GPIO, UART1_TX_PIN_SOURCE, GPIO_AF_USART1);
+    GPIO_PinAFConfig(UART1_GPIO, UART1_RX_PIN_SOURCE, GPIO_AF_USART1);
+#endif /* RT_USING_UART1 */
+
+#ifdef RT_USING_UART2
+    /* Configure USART2 Rx/tx PIN */
+    GPIO_InitStructure.GPIO_Pin = UART2_GPIO_RX | UART2_GPIO_TX;
+    GPIO_Init(UART2_GPIO, &GPIO_InitStructure);
+
+    /* Connect alternate function */
+    GPIO_PinAFConfig(UART2_GPIO, UART2_TX_PIN_SOURCE, GPIO_AF_USART2);
+    GPIO_PinAFConfig(UART2_GPIO, UART2_RX_PIN_SOURCE, GPIO_AF_USART2);
+#endif /* RT_USING_UART2 */
+
+#ifdef RT_USING_UART3
+    /* Configure USART3 Rx/tx PIN */
+    GPIO_InitStructure.GPIO_Pin = UART3_GPIO_TX | UART3_GPIO_RX;
+    GPIO_Init(UART3_GPIO, &GPIO_InitStructure);
+
+    /* Connect alternate function */
+    GPIO_PinAFConfig(UART3_GPIO, UART3_TX_PIN_SOURCE, GPIO_AF_USART3);
+    GPIO_PinAFConfig(UART3_GPIO, UART3_RX_PIN_SOURCE, GPIO_AF_USART3);
+#endif /* RT_USING_UART3 */
+}
+
+static void NVIC_Configuration(struct stm32_uart *uart)
+{
+    NVIC_InitTypeDef NVIC_InitStructure;
+
+    /* Enable the USART1 Interrupt */
+    NVIC_InitStructure.NVIC_IRQChannel = uart->irq;
+    NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 3;
+    NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+    NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+    NVIC_Init(&NVIC_InitStructure);
+}
+
+int stm32_hw_usart_init(void)
+{
+    struct stm32_uart *uart;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+    RCC_Configuration();
+    GPIO_Configuration();
+
+#ifdef RT_USING_UART1
+    uart = &uart1;
+
+    serial1.ops    = &stm32_uart_ops;
+    serial1.config = config;
+
+    NVIC_Configuration(&uart1);
+
+    /* register UART1 device */
+    rt_hw_serial_register(&serial1,
+                          "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+#endif /* RT_USING_UART1 */
+
+#ifdef RT_USING_UART2
+    uart = &uart2;
+
+    serial2.ops    = &stm32_uart_ops;
+    serial2.config = config;
+
+    NVIC_Configuration(&uart2);
+
+    /* register UART1 device */
+    rt_hw_serial_register(&serial2,
+                          "uart2",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+#endif /* RT_USING_UART2 */
+
+#ifdef RT_USING_UART3
+    uart = &uart3;
+
+    serial3.ops    = &stm32_uart_ops;
+    serial3.config = config;
+
+    NVIC_Configuration(&uart3);
+
+    /* register UART3 device */
+    rt_hw_serial_register(&serial3,
+                          "uart3",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+#endif /* RT_USING_UART3 */
+
+    return 0;
+}
+INIT_BOARD_EXPORT(stm32_hw_usart_init);

demos/os/rtthread/stm32f4xx/components/rtt_uart/usart.h

@@ -0,0 +1,26 @@
+/*
+ * File      : usart.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      the first version
+ */
+
+#ifndef __USART_H__
+#define __USART_H__
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#define UART_ENABLE_IRQ(n)            NVIC_EnableIRQ((n))
+#define UART_DISABLE_IRQ(n)           NVIC_DisableIRQ((n))
+
+int stm32_hw_usart_init(void);
+
+#endif